1. Field of the Invention
The present invention relates to a digital Phase-Locked Loop (PLL)/Frequency-Locked Loop (FLL). More particularly, the present invention relates to an apparatus and method for compensating for a phase difference generated when a phase jump occurs in a reference signal.
2. Description of the Related Art
A digital Phase-Locked Loop (PLL)/Frequency-Locked Loop (FLL) is a widely used function in a communication field to synchronize an internal clock signal with an external clock signal (i.e., a reference signal).
In a conventional PLL/FLL implementation, the reference signal is obtained from an upper-layer system over an E1/T1 network. In this case, Bit Justification (BJ) and Pointer Adjustment (PA) occur, which result in jitter and phase jump of the reference signal and affects PLL/FLL performance. Therefore, in order to ensure adequate PLL/FLL performance, there is a need to compensate for phase jump of the reference signal. However, the conventional PLL/FLL implementation cannot provide a compensation function that sufficiently compensates for the phase jump.